KAIST Researchers Predict Transistor Scaling Limits Using Atom-Level Simulations
Researchers at KAIST have developed a new technology to predict the ultimate scaling limits of transistors, which are core components of semiconductor chips. This advancement comes as the global semiconductor industry transitions into the 2-nanometer process era, despite the actual size of transistors currently remaining above 10 nanometers. The developed technology utilizes quantum mechanical, atom-level calculations to forecast how much smaller transistors can become.
The global semiconductor industry is advancing into what is known as the 2-nanometer process era. Despite this development, the actual physical size of transistors, which are fundamental components within semiconductor chips, still measures above 10 nanometers.
Addressing the question of how much further transistors can be miniaturized, researchers at KAIST have introduced a new methodology. This technology is designed to predict the scaling limits for these crucial electronic components.
The predictive capability is achieved through the use of quantum mechanical, atom-level calculations. This approach allows for a detailed understanding of the physical constraints that dictate the minimum achievable size for transistors.
According to Phys.org, this research provides a tool for the semiconductor industry to better understand future design possibilities.
